If verilog doesn't allow declaration/passing of multidimensional arrays in module's portlist, is there a workaround it? Lets say i have an array like array[27:0][64:0]. How can we pass it into a module? (like making it as 1d array and do some reversal on the module body) I think the only way is to pass it as 1 dimensional and do some mechanisms to reference like the original multidimentional one. Thanks. I researched a while ago, and that feature is available in SystemVerilog but not in the original Verilog.
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As the initial commenter pointed out that in SystemVerilog what you're asking for is explicitly supported. You can even pass structs through module boundaries.
However, if you're stuck with old style Verilog then the way to do is just as you guessed. Flatten it out into a 1D array and blow it back out inside the module.
In psuedo-code
input [WIDTH * DEPTH - 1:0] in;
reg [WIDTH - 1:0] array [0:DEPTH - 1];
integer i;
for (i = 0; i < DEPTH; i = i + 1)
array = in[i * WIDTH +: WIDTH];
With a similar packing for-loop on the other side of the module boundary. The +: syntax is nice but it you even don't have access to that then you can convert it to explicit bounds fairly easily.
1 Comment
Brian Magnuson
Even without +: you can do this without an inner loop. in[(i + 1) * WIDTH - 1 : (i * WIDTH)]