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I am trying to compile SystemVerilog code that will generate an output on a 4-digit 7-segment display based on two buttons. I was given the hint to use a concatenation operator but kept getting a "Can't resolve multiple constant drivers" error. I believe this meant there were multiple assignments to the same signal. I corrected this by removing the latter 3 assign statements and using an array instead, but I am not sure on how the syntax would work for having two outputs in each register. Adding brackets did not work.

  (
     output logic [3:0]en, //7 segment digit selector
     output logic a,b,c,d,e,f,g,  //7 segment display
     input logic [1:0] x  //button input
  );

    logic [3:0] lut [4] = {(4'b1000,7'h01), (4'b0100,7'h04), (4'b0010,7'h01),(4'b001,7'h01)};
    assign [en,a,b,c,d,e,f,g] = lut[x]

    //this was my original code
    //assign {en,a,b,c,d,e,f,g} = x == 2'b11 ? {4'b1000,7'h01}:0;
    //assign {en,a,b,c,d,e,f,g} = x == 2'b10 ? {4'b0100,7'h0f}:0;
    //assign {en,a,b,c,d,e,f,g} = x == 2'b01 ? {4'b0010,7'h01}:0;
    //assign {en,a,b,c,d,e,f,g} = x == 2'b00 ? 0:{4'b0001,7'h01};

1 Answer 1

1

A case statement is commonly used in such situations:

module disp
  (
     output logic [3:0]en, //7 segment digit selector
     output logic a,b,c,d,e,f,g,  //7 segment display
     input logic [1:0] x  //button input
  );

always_comb begin
    case (x)
        2'b11 : {en,a,b,c,d,e,f,g} = {4'b1000,7'h01};
        2'b10 : {en,a,b,c,d,e,f,g} = {4'b0100,7'h0f};
        2'b01 : {en,a,b,c,d,e,f,g} = {4'b0010,7'h01};
        2'b00 : {en,a,b,c,d,e,f,g} = {4'b0001,7'h01};
    endcase
end

endmodule

You are correct: you can not use the assign keyword multiple times to the same signal.


Here is a version with an array which simulates the same as the case:

module disp
  (
     output logic [3:0]en, //7 segment digit selector
     output logic a,b,c,d,e,f,g,  //7 segment display
     input logic [1:0] x  //button input
  );

    logic [10:0] lut [4] = {{4'b001,7'h01}, {4'b0010,7'h01}, {4'b0100,7'h0f}, {4'b1000,7'h01}};

always_comb begin
    {en,a,b,c,d,e,f,g} = lut[x];
end

endmodule

I rearranged the values in the array to match the case.

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