How to initialize parameter array in verilog?

Question

How can one initialize parameter type array in verilog where each of members are 32 bit hexadecimal notation numbers? I have tried the following but it gives me syntax error.

parameter [31:0] k[0:63] = {32'habc132, 32'hba324f, ...};

I'm using latest version of iverilog for compiling.

Verilog-1995 doesn't support arrayed parameters. Verilog-2005 does but it the LRM is not explicit about multidimensional parameter arrays, it should support it. All version of SystemVerilog does support it, some require '{} to define the array. — Greg
– Greg, Commented Oct 10, 2014 at 21:33
@Greg You are correct. Seems like my compiler doesn't support it. — The amateur programmer
– The amateur programmer, Commented Oct 11, 2014 at 9:34

Morgan · Accepted Answer · 2014-10-10 17:16:53Z

4

On EDA Plyground The following example works using modelsim 10.1, the file has a .sv extension, causing it to be interpreted as SystemVerilog:

module test;
parameter [31:0] k [0:1] = {32'habc132, 32'hba324f};

  initial begin
    $displayh(k[0]);
    $displayh(k[1]);
  end
endmodule

If setting to SystemVerilog does not work or is not available for your simulator I suggest including the syntax error in the question.

answered Oct 10, 2014 at 17:16

Morgan

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