How to flatten array in Verilog

Question

As Verilog does not allow to pass the array as input to module, so how can we flatten any array in Verilog. Suppose I have this array:

parameter [31:0] A [0:31];
wire [31:0] B

I want to pass this into any module like:

module1 M1 (.input(A), .output (B));

How can I achieve this?

Sorry about my misunderstading, I am not clear about flatten array. Can you describe it more. On the other hand, if you map parameter, it should be module #(.para(A)) M1 (.output(B)); . I do not think map parameter as InputOutput is legal. — Khanh N. Dang
– Khanh N. Dang, Commented Feb 20, 2015 at 7:44
As my best understand, you should use generate to convert A to one dimensional array to map. — Khanh N. Dang
– Khanh N. Dang, Commented Feb 20, 2015 at 7:47
@KhanhN.Dang By flattening I mean converting it into 1D. For example I have array {1,2,3,4,5}; I want to pass each member one by one into module. Hope it helps to understand the problem — Awais Hussain
– Awais Hussain, Commented Feb 20, 2015 at 9:48
I would like to go with the method given below. If I have large array of thousand members then it will be taking a lot of clock cycles... But it would be good to know about array passing on clock for knowledge. — Awais Hussain
– Awais Hussain, Commented Feb 20, 2015 at 12:57
If you have large array containing thousands elements each of multiple bits you will have a very large bus. It is not likely to fit on an FPGA and closing timing would be very problematic. — Morgan
– Morgan, Commented Feb 20, 2015 at 13:19

grorel · Accepted Answer · 2015-02-20 17:03:30Z

4

This verilog restriction is just a pain in... and etc... but we have to deal with it.

You can map the 2D array onto a 1D array like this :

wire [32*32-1:0]One_D_array;
integer i;
for (i=0; i<32; i=i+1) assign One_D_array[32*i+31:32*i] = A[i];

Then in your module, you can recreate the 2D array with the inverted for loop :

wire [31:0]local_2D_array[0:31];
integer i;
for (i=0;i<32;i=i+1) assign local_2D_array[i] = input[32*i+31:32*i];

The synthesis tool will handle it as wire remapping, so no LUT/FLIP_FLOP will be used. This is the easiest workaround I found for this limitation.

edited Feb 20, 2015 at 17:03

answered Feb 20, 2015 at 12:10

grorel

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6 Comments

Morgan Over a year ago

SystemVerilog can have array style ports.

grorel Over a year ago

Indeed. This answer applies for verilog only.

Awais Hussain Over a year ago

I am trying to implement 1st part of code that is making 2D into 1D. Here is code: module Array_passing_testing( input clk ); parameter [31:0] A[0:31]= {1,2,3,4,5,6,7,8,9,10,11,12,1,2,3,4,5,6,7,8,9,10,11,12,1,2,3,4,5,6,7,8}; wire [32*32-1:0]One_D_array; genvar i; for (i=0; i<7; i=i+1) assign #10 One_D_array[32*i-1:32*i] = A[i]; endmodule But it is giving following error: Part-select direction is opposite from prefix index direction.

Awais Hussain Over a year ago

Sorry for bad formatting. I tried to edit it but 5 minutes had passed and 4 spaces for codes didn't work

Morgan Over a year ago

@AwaisHussain try reversing the bit range instead of [32*i-1:32*i] try [32*i:32*i-1].

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