unpacking a vector into an array in verilog using for loops

Question

Problem: I have N elements of X bits each, and have them concatenated into 1 vector and now I want to unpack them into a matrix M[N][X] using for loops. For example,

input [N*X-1:0]VECTOR;
integer i;
reg [X-1:0]M[N-1:0];
always@(*) begin
    for(i=0; i<N; i=i+1) begin
        M[i] = VECTOR[(X*(i+1)-1):(X*i)];
    end
end

However, the above code gives me the following error:

Error (10734): Verilog HDL error at FILE.v(line_number): i is not a constant

Community · Accepted Answer · 2017-05-23 11:44:28Z

1

A few corrections:

input [N*X-1:0] VECTOR; // move range to the other side
integer i;
reg [X-1:0] M [0:N-1]; // Give proper range with X
always @* begin // always block for comb logic
  for(i=0; i<N; i=i+1) begin // not i=i++
    M[i] = VECTOR[X*i +: X]; // vector slicing
  end
end

Refer to previously answered questions to explain +: vector slicing:

edited May 23, 2017 at 11:44

CommunityBot

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answered Sep 17, 2015 at 17:20

Greg

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