Systemverilog error: Illegal range in part select

Question

I am trying to achieve this and during elab i see error : Illegal range in part select

logic  [1:0] buffer_value;
logic  [1:0] temp;
logic  [23:0] pad;
logic  [23:0] shift_out;

 always_comb
    begin
        temp = buffer_value;
        pad = {shift_out[temp*8-1:0], shift_reg[(3-temp)*8-1:0]};
    end

i understand the issue that SV is unable to comeup with the range because of using variable on shift_out size. Is there a way to do this. Thanks

dave_59 · Accepted Answer · 2022-08-21 17:44:02Z

1

You need to use a mask, shift and bitwise-or approach

let mask(value, select) = (2**select-1 & value);
int sel1, sel2;
always_comb
    begin
        temp = buffer_value;
        sel1 = temp*8;
        sel2 = (3-temp)*8
        pad = mask(shift_out,sel1) << sel2 | mask(shift_reg,sel2);
    end

answered Aug 21, 2022 at 17:44

dave_59

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2 Comments

Kavitha Modem Over a year ago

Thanks Dave for the solution. i did make use of the shifting to address the issue. But i dont understand the use of masking in this case. Example: if temp[1:0]=2'b01 then sel1=8, sel2=16. mask(value,sel1) would expand value to 16 bits and shifting left by 16 (sel2) would be something incorrect. I tried with temp=2, things dont add up. But i get the concept of shifting for this use case which i could make of. Thank you.

dave_59 Over a year ago

If temp=1, then you want pad = {shift_out[7:0], shift_reg[15:0]}; That means you want shift_out[0] to be assigned to pad[16] so you need to shift by 16.

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