Verilog assign part of array memory

Question

I've trying to define some part of a memory array in Verilog such as this one

module test (
  input clk,
  input [7:0]  in1,
  input [23:0] in2
);

wire [7:0] array_in2 [2:0];
reg  [7:0] buffer    [5:0];

genvar i;

generate
  for (i = 0; i < 3; i = i + 1) begin: fillmsg
    assign array_in2[i] = in2[i*8 +:8];
  end
endgenerate

always @(posedge clk) begin
  //buffer <= {8'd0, in1, 8'd1, array_in2}; // does not work
  buffer[0] <= 8'd0;
  buffer[1] <= in1;
  buffer[2] <= 8'd1;
  buffer[5:3] <= array_in2; // <--- does not work either
end

endmodule

but I haven't been successful. Does anyone have an idea how this assignment could be done?

EDIT:

As dave_59 suggested one way to do the assignment would be one array element at a time

integer j;
always @(posedge clk) begin
  for (j=0; j<3; j=j+1) begin
    buffer[i+3] <= array_in2[i];
  end
end

dave_59 · Accepted Answer · 2018-08-27 15:35:39Z

2

Verilog does not allow operations on more than one array element at a time. You need to move to SystemVerilog for your code to work. Just changing the file extension to *.sv is usually all you need to do. Then both your assignments should work.

answered Aug 27, 2018 at 15:35

dave_59

43.3k3 gold badges29 silver badges66 bronze badges

Sign up to request clarification or add additional context in comments.

Collectives™ on Stack Overflow

Verilog assign part of array memory

1 Answer 1

Comments

Your Answer

Hot Network Questions

Collectives™ on Stack Overflow

1 Answer 1

Comments

Your Answer

Sign up or log in

Post as a guest

Related