I recently started System Verilog and I'm a bit dumbfounded by a syntax error. Given the following module:
test.sv :
module test(
input logic clk,
output logic out );
always_ff @(posedge clk) begin
out = 1'b1;
end
endmodule
When compiling with iverilog -g2012 test.sv, a simple syntax-error for line 5 (always_ff) is generated. I don't know why this happens since my syntax seems to be correct.
The syntax is correct for SystemVerilog, but it is not supported for all iverilog versions. From the Release Notes of Icarus Verilog 11
The following SystemVerilog language features are now supported:
the always_comb, always_ff, and always_latch constructs
If you are not using this version, you should upgrade.
Your code compiles on other simulators on edaplayground.
Alternately, you don't need to use always_ff. You can still use always:
always @(posedge clk) begin
out <= 1'b1;
end
I changed your assignment to nonblocking (<=), which is recommended for sequential logic.
